US 10,043,808 B1Granted

Semiconductor memory

AssigneeToshiba Memory Corporation

InventorsTsutomu Tezuka, Fumitaka Arai, Keiji Ikeda, Tomomasa Ueda, Nobuyoshi Saito, Chika Tanaka, Kentaro Miura

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Abstract

According to one embodiment, a semiconductor memory includes: a first gate of a first select transistor and a second gate of a second select transistor on a gate insulating film on a semiconductor layer; an oxide semiconductor layer above the semiconductor layer; a first control gate of a first cell and a second control gate of a second cell on an insulating layer on the oxide semiconductor layer; a third gate of a first transistor between the first control gate and the second control gate; a fourth gate of a second transistor between a first end of the oxide semiconductor layer and the second control gate; an interconnect connected to the first end; a source line connected to the first select transistor; and a bit line connected to the second select transistor.

Claims19

Dependent claims

A semiconductor memory comprising:

a semiconductor layer;
a gate insulating film on the semiconductor layer;
a first gate electrode of a first select transistor on the gate insulating film;
a second gate electrode of a second select transistor on the gate insulating film;
an oxide semiconductor layer disposed above the semiconductor layer between the first and second select transistors via the gate insulating film;
an insulating layer on the oxide semiconductor layer;
a first control gate electrode of a first memory cell on the insulating layer;
a second control gate electrode of a second memory cell on the insulating layer;
a third gate electrode of a first transistor on the insulating layer between the first control gate electrode and the second control gate electrode;
a fourth gate electrode of a second transistor on the insulating layer between a first end of the oxide semiconductor layer and the second control gate electrode;
a first interconnect connected to the first end of the oxide semiconductor layer;
a source line connected to a first terminal of the first select transistor;
and
a bit line connected to a second terminal of the second select transistor.

11 more elements

A semiconductor memory comprising:

a pillar disposed on a substrate and extending in a first direction, the pillar including an oxide semiconductor layer;
a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the substrate along the first direction and opposite to a side surface of the pillar;
a select transistor disposed at an intersection of the first conductive layer and the pillar;
a first memory cell disposed at an intersection of the second conductive layer and the pillar;
a first transistor disposed at an intersection of the third conductive layer and the pillar;
a second memory cell disposed at an intersection of the fourth conductive layer and the pillar;
a second transistor disposed at an intersection of the fifth conductive layer and the pillar;
a bit line connected to a first end of the pillar in the first direction;
a source line connected to a second end of the pillar in the first direction;
and
an interconnect connected to the oxide semiconductor layer.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/705,457Filed 15 Sep 2017
Priority: JP 2017-05138816 Mar 2017
Granted: 7 Aug 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 30/69
Insulated-gate field-effect transistors [IGFET]: iGFETs having charge trapping gate insulators, e.g. MNOS transistors
G11C 11/4097
Read-write [R-W] circuits: bit-line organisation, e.g. bit-line layout, folded bit lines
G11C 16/0408
Using variable threshold transistors, e.g. FAMOS: comprising cells containing floating gate transistors
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits