Incremental preloading in an analog-to-digital converter
AssigneeAnalog Devices, Inc.
InventorsBaozhen Chen, Edward C. Guthrie, Michael C. W. Coln, Mark D. Maddox
Life of this patent
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Abstract
During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.
Claims20
A method of improving digital-to-analog converter (DAC) resolution in a DAC including a thermometer encoded array having logically adjacent capacitive cells corresponding to different bit positions of an input digital control word by temporally ordering the sequential loading of capacitive cells in the DAC to reduce transient out-of-range voltages and associated loss of signal charge, the method comprising:
- loading onto a first cell having a logical position in the array of capacitive cells determined by a logical midpoint of the thermometer encoded array, a charge associated with a decoded most significant bit (MSB) decision;
- and
- then loading onto a second cell on a first logical side of the logical midpoint, a charge associated with a decoded second bit decision, and loading onto a third cell on a second logical side of the logical midpoint different from the first logical side, a charge associated with a decoded third bit decision.
A system for improving digital-to-analog converter (DAC) resolution in a DAC including a thermometer encoded array having logically adjacent capacitive cells corresponding to different bit positions of an input digital control word by temporally ordering the sequential loading of capacitive cells in the DAC to reduce transient out-of-range voltages and associated loss of signal charge, the system comprising:
- a first cell having a logical position in an array of capacitive cells determined by a logical midpoint of the thermometer encoded array;
- a second cell on a first logical side of the logical midpoint and a third cell on a second logical side of the logical midpoint different from the first logical side;
- and
- control circuitry configured to (i) load a charge associated with a decoded most significant bit (MSB) decision onto the first cell, and (ii) then load a charge associated with a decoded second bit decision onto the second cell and load a charge associated with a decoded third bit decision onto the third cell.
Dependencies are inferred from the claim text.