Through-memory-level via structures for a three-dimensional memory device

A semiconductor structure comprising:

• a memory-level assembly located over a semiconductor substrate and comprising at least one first alternating stack of electrically conductive layers and first portions of insulating layers, and further comprising memory stack structures vertically extending through the at least one first alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel, wherein the electrically conductive layers comprise word lines for the memory stack structures;
• an insulating moat trench structure vertically extending through the memory-level assembly and defining an area of a through-memory-level via region laterally spaced from the at least one first alternating stack;
• at least one second alternating stack located in the through-memory-level via region, wherein the at least one second alternating stack includes alternating layers of dielectric spacer layers and second portions of the insulating layers, and each of the dielectric spacer layers is located at a same level as a respective electrically conductive layer;
• and
• through-memory-level via structures located within the through-memory-level via region and comprising a conductive material.