Apparatus and method for vector instructions for large integer arithmetic

A method comprising:

• decoding a first instruction into a decoded first instruction, a second instruction into a decoded second instruction, and an add instruction into a decoded add instruction with a hardware decoder of a hardware processor;
• executing the decoded first instruction with a hardware execution unit of the hardware processor to multiply a first input operand and a second input operand and store a lower portion of a result, said first and second input operands being respective elements of a first input vector and a second input vector;
• executing the decoded second instruction with the hardware execution unit of the hardware processor to multiply the first input operand and the second input operand and store an upper portion of a result, said first and second input operands being the respective elements of the first input vector and the second input vector;
• and
• executing the decoded add instruction with the hardware execution unit of the hardware processor to add aligned elements of the upper portion and the lower portion with a previous, corresponding carry term from an input operand and store a result.

A non-transitory machine readable medium containing program code that when processed by a processing unit causes a method to be performed, said method comprising:

• decoding a first instruction into a decoded first instruction, a second instruction into a decoded second instruction, and an add instruction into a decoded add instruction with a hardware decoder of a hardware processor;
• executing the decoded first instruction with a hardware execution unit of the hardware processor to multiply a first input operand and a second input operand and store a lower portion of a result, said first and second input operands being respective elements of a first input vector and a second input vector;
• executing the decoded second instruction with the hardware execution unit of the hardware processor to multiply the first input operand and the second input operand and store an upper portion of a result, said first and second input operands being the respective elements of the first input vector and the second input vector;
• and
• executing the decoded add instruction with the hardware execution unit of the hardware processor to add aligned elements of the upper portion and the lower portion with a previous, corresponding carry term from an input operand and store a result.