Method for forming stacked nanowire transistors

A method comprising:

• forming, on a substrate, first semiconductor stack features, each of the first semiconductor stack features comprising a first plurality of semiconductor layers and a second plurality of semiconductor layers that are alternatingly stacked along a first direction perpendicular to a top surface of the substrate, the first plurality of semiconductor layers comprising a first semiconductor material and the second plurality of semiconductor layers comprising a second semiconductor material that is different from the first semiconductor material;
• forming isolation features between the first semiconductor stack features;
• removing at least one of the first semiconductor stack features, thereby forming at least one trench;
• and
• forming, on the substrate and within the at least one trench, second semiconductor stack features, each of the second semiconductor stack features comprising a third plurality of semiconductor layers and a fourth plurality of semiconductor layers that are alternatingly stacked along the first direction, the third plurality of semiconductor layers comprising a third semiconductor material and the fourth plurality of semiconductor layers comprising a fourth semiconductor material that is different from the third semiconductor material.

A method of forming a semiconductor device, the method comprising:

• forming first semiconductor features, each of the first semiconductor features comprising first semiconductor layers and second semiconductor layers that are alternatingly arranged along a first direction perpendicular to a top surface of a substrate, the first semiconductor features comprising a first set of characteristics;
• forming isolation features between the first semiconductor features;
• removing at least one of the first semiconductor features, thereby forming at least one trench;
• and
• forming, within the at least one trench, at least one second semiconductor feature comprising third semiconductor layers and fourth semiconductor layers that are alternatingly arranged along the first direction, the at least one second semiconductor feature comprising a second set of characteristics that is different from the first set of characteristics.