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US 10,027,600 B2Granted
Time-division multiplexing data aggregation over high speed serializer/deserializer lane
AssigneeArtesyn Embedded Computing, Inc.
InventorsStephan Kruecker, Armin Jacht, Reinhold Hofer
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Abstract
A digital signal interface includes a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data signals. The interface further includes a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals.
Claims13
A digital signal interface, comprising:
- a multiplexer coupled to receive a plurality time division multiplexed (TDM) data signals from a corresponding plurality of digital signal processors (DSP) comprising a DSP farm located on a front board of a telecommunications processing device connected to a rear transition module via a backplane, the multiplexer multiplexing the plurality of parallel data signals, wherein the data signal output by each DSP includes a plurality of output signal lines communicating signals in parallel;
- and
- a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed plurality of TDM data signals, the SerDes transceiver serializing the multiplexed plurality of TDM data signals and transmitting the serialized data signals to the rear transition module, the rear transition module including a timeslot interchange (TSI) switch, receiving the serialized data
- wherein each data signal includes a pair of serial clock signals and a pair of frame synchronization signals for receiving and transmitting the parallel data signals.
1 more element
A digital signal interface, comprising:
- a multiplexer coupled to receive a plurality of time division multiplexed (TDM) data signals from a corresponding plurality of digital signal processors (DSP) comprising a DSP farm located on a front board of a telecommunications processing device connected to a rear transition module via a backplane, the multiplexer multiplexing the plurality of data signals, wherein the data signal output by each DSP includes a plurality of output signal lines communicating signals in parallel;
- and
- a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed plurality of TDM data signals, the SerDes transceiver serializing the multiplexed plurality of TDM data signals and transmitting the serialized data signals to the rear transition module, the rear transition module including having a timeslot interchange (TSI) switch receiving the serialized data,
- wherein the front board of the telecommunications processing device communicates using a time-division multiplexing (TDM) bus protocol,
- wherein each data signal includes a pair of serial clock signals and a pair of frame synchronization signals.
2 more elements
Dependencies are inferred from the claim text.