Low-stress low-hydrogen LPCVD silicon nitride
AssigneeTexas Instruments Incorporated
InventorNicholas Stephen Dellas
Life of this patent
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Abstract
A microelectronic device contains a high performance silicon nitride layer which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent, formed by an LPCVD process. The LPCVD process uses ammonia and dichlorosilane gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800° C. to 820° C.
Claims13
A Gallium-Nitride Field Effect Transistor (GaN FET) device, comprising:
- a stack of gallium nitride and aluminum gallium nitride layers as a substrate;
- a cap layer of gallium nitride on the stack;
- a silicon nitride layer on a first surface of the cap layer, the silicon nitride layer having the following properties:
- a silicon:nitrogen atomic ratio within 2 percent of the ratio 3:4;
- a stress of 600 megapascals (MPa) to 1000 MPa;
- and
- a hydrogen content of less than 5 atomic percent;
- and
- a gate of the GaN FET over the cap layer, wherein the gate is in direct contact with the first surface of the cap layer at a center portion of the gate and partially overlaps the silicon nitride layer at end portions of the gate.
A Gallium-Nitride Field Effect Transistor (GaN FET) device, comprising:
- a stack of gallium nitride and aluminum gallium nitride layers as a substrate;
- a cap layer of gallium nitride on the stack;
- a silicon nitride layer on a first surface of the cap layer, the silicon nitride layer having the following properties:
- a silicon:nitrogen atomic ratio within 2 percent of the ratio 3:4;
- a stress of 600 megapascals (MPa) to 1000 MPa;
- and
- a hydrogen content of less than 5 atomic percent;
- a source and a drain, wherein the silicon nitride layer is located between the source and drain;
- and
- a gate of the GaN FET over the cap layer between the source and drain, wherein the gate is in direct contact with the first surface of the cap layer at a center portion of the gate and partially overlaps the silicon nitride layer at end portions of the gate.
A Gallium-Nitride Field Effect Transistor (GaN FET) device, comprising:
- a stack of gallium nitride and aluminum gallium nitride layers;
- a cap layer of gallium nitride on the stack;
- a silicon nitride layer on the cap layer, the silicon nitride layer having the following properties:
- a silicon:nitrogen atomic ratio within 2 percent of the ratio 3:4;
- a stress of 600 megapascals (MPa) to 1000 MPa;
- and
- a hydrogen content of less than 5 atomic percent;
- a source and a drain;
- a gate of the GaN FET over the cap layer between the source and drain, wherein the gate is in direct contact with the cap layer at a center portion of the gate and partially overlaps the silicon nitride layer at end portions of the gate;
- a source metal in electrical contact with a contact metal of the source, the source metal overlapping the gate;
- and
- a dielectric layer between the source metal and the gate, wherein the silicon nitride includes a first portion under the end portions of the gate and a second portion between the gate and the drain spaced from both the drain and the gate.
Dependencies are inferred from the claim text.