Techniques for variable latency redundancy
AssigneeIntel Corporation
InventorsMartin Langhammer, Dongdong Chen, Jung Ko
Life of this patent
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AssigneeIntel Corporation
InventorsMartin Langhammer, Dongdong Chen, Jung Ko
Estimating the term…
An integrated circuit includes first and second circuit blocks. The first circuit block includes a first storage circuit. A first data path passes through the first storage circuit and a first multiplexer circuit to a first input of a first logic circuit. The first multiplexer circuit is coupled to the first storage circuit. A second storage circuit is coupled between the first storage circuit and the first multiplexer circuit. A second data path passes through the second circuit block to a second input of the first logic circuit. The first multiplexer circuit is configurable to bypass or to couple the second storage circuit in the first data path based on an indication of whether a redundant third circuit block is coupled between the first and second circuit blocks in at least one of the first data path or the second data path.
An integrated circuit comprising:
A method for providing variable latency redundancy, the method comprising:
A computer-readable non-transitory medium storing executable instructions for providing variable latency redundancy to circuit blocks in an integrated circuit, the executable instructions comprising:
Dependencies are inferred from the claim text.