Digital filter
AssigneeIntel Deutschland GmbH
InventorAndreas Menkhoff
Life of this patent
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Abstract
A first stage of a digital filter received input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and (2) the first clock pulse of the first clock.
Claims16
An apparatus, comprising:
- a first stage to receive an input, the first stage including:
- a register, at most two multipliers, at least two adders, coupled together to provide first and second inputs in response to the received input;
- a first sampler to receive the first input and to sample it to provide a first sampled input;
- a second sampler to receive the second input and to sample it to provide a second sampled input;
- and
- a second stage including an adder and a register which are to receive the first and second sampled inputs, respectively, and to generate an output, wherein one or more of the register, at most two multipliers, or at least two adders of the first stage is to operate on a first frequency, and wherein one or more of the adder or the register of the second stage is to operate on a second frequency different from the first frequency.
A method comprising:
- receiving an input by a first stage, wherein the first stage includes:
- a register, at most two multipliers, and at least two adders, coupled together to provide first and second inputs in response to the received input;
- sampling the first input to provide a first sampled input;
- sampling the second input to provide a second sampled input;
- and
- receiving by a second stage the first and second sampled inputs and to generate an output, wherein one or more of the register, at most two multipliers, or at least two adders of the first stage is to operate on a first frequency, and wherein one or more circuitries of the second stage is to operate on a second frequency different from the first frequency.
An apparatus comprising:
- a first stage to receive an input, the first stage including at most two multipliers, the first stage is to provide first and second inputs in response to the received input;
- and
- a first sampler to receive the first input and to sample it to provide the sampled version of the first input as a first sampled input;
- a second sampler to receive the second input and to sample it to provide the sampled version of the second input as a second sampled input, and
- a second stage including an adder and a register which are to receive sampled versions of the first and second inputs, respectively, and to generate an output,
- wherein the adder or register of the second stage is coupled in a feedback mechanism such that the output is to be input to the adder,
- wherein the first stage is to operate on a first frequency, wherein the second stage is to operate on a second frequency, and wherein the first frequency is lower than the second frequency.
Dependencies are inferred from the claim text.