# US 10,007,639 B2 · PLL system with master and slave devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,007,639 B2 - Document ID: US10007639B2 - Status: Granted - Kind: B2 - Application number: 15/090,637 - Filed: 2016-04-05 - Published: 2016-10-13 - Granted: 2018-06-26 - Earliest claimed: 2015-04-08 - Assignees: Microsemi Semiconductor ULC - Applicants: Microsemi Semiconductor ULC - Inventors: Krste Mitric; Slobodan Milijevic; Wenbao Wang; Gabriel Rusaneanu - Web page: https://patentgrep.com/patent/US10007639B2 ## CPC - G06F 13/4291: {using a clocked protocol} - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 13/364: using independent requests or grants, e.g. using separated request and grant lines - H03L 7/099: concerning mainly the controlled oscillator of the loop - H03L 7/16: Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop - H03L 7/22: using more than one loop - H03L 2207/06: Phase locked loops with a controlled oscillator having at least two frequency control terminals - H03L 2207/50: All digital phase-locked loop - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A master phase locked loop device is operable in association with one or more slave devices including slave digitally controlled oscillators (sDCOs), one or more digital PLL (DPLL) channels include a master digitally controlled oscillator (mDCO). A master synchronization timer generating master timing pulses to read phase and frequency information from the mDCO(s). A peripheral interface sends the read frequency and phase information to the one or more slave devices. A synchronization interface sends the master timing pulses to synchronize a replica synchronization timer in the sDCO(s) that generates slave timing pulses for use in updating the phase and frequency information received at the slave device(s). ## Claims ### Claim 1 A master phase locked loop device arranged for operation in association with one or more slave devices each comprising a respective slave digitally controlled oscillator (sDCO), the master phase locked loop device comprising: at least one digital PLL (DPLL) channel, each including a master digitally controlled oscillator (mDCO) having a higher resolution than said respective DCOs of the one or more slave devices; a master synchronization timer for generating master timing pulses to permit reading phase and frequency information from said mDCO; a peripheral interface for sending said read phase and frequency information to said one or more slave devices; and a master synchronization interface for sending said master timing pulses to synchronize a respective replica synchronization timer in each of said one or more slave devices, the respective replica synchronization timer arranged to generate slave timing pulses for use in updating the respective sDCO of the respective slave device with said read phase and frequency information received at the respective slave device. ### Claim 2 (depends on 1) The master phase locked loop device as claimed in claim 1, wherein said peripheral interface is a serial interface. ### Claim 3 (depends on 1) The master phase locked loop device as claimed in claim 1, further comprising a multiplexer for selecting one of a plurality of reference clocks for input to said at least one DPLL channel. ### Claim 4 (depends on 1) The master phase locked loop device as claimed in claim 1, wherein the at least one DPLL channel is one of a plurality of DPLL channels. ### Claim 5 (depends on 4) The master phase locked loop device as claimed in claim 4, wherein a selected one of the plurality of DPLL channels is designated as a feedback calibration channel and is responsive to a feedback signal from a selected one of said one or more slave devices to effect fine adjustment of the respective sDCO included in said selected slave device. ### Claim 6 (depends on 5) The master phase locked loop device as claimed in claim 5, further comprising a delay control module responsive to the feedback signal to update the mDCO of the other DPLL channels in the master phase locked loop device. ### Claim 7 (depends on 6) The master phase locked loop device as claimed in claim 6, further comprising a multiplexer responsive to selection signals to select a slave output clock from said selected slave device for input to said feedback calibration channel. ### Claim 8 (depends on 7) The master phase locked loop device as claimed in claim 7, wherein said multiplexer is configured to select the slave output clock from said one or more slave devices in turn in a time division multiplexed manner. ### Claim 9 (depends on 7) The master phase locked loop device as claimed in claim 7, further comprising a general purpose input/output (GPIO) controller operative to send said selection signals to said multiplexer. ### Claim 10 (depends on 1) The master phase locked loop device as claimed in claim 1, wherein said master synchronization interface generates said master timing pulses with a width that is wide enough to guarantee correct sampling by said one or more slave devices. ### Claim 11 A slave device operating in association with a master phase locked loop (PLL) device and running on a system clock generated in said master PLL device, comprising: a slave digitally controlled oscillator controlled by phase and frequency information obtained from the master PLL device; and a replica synchronization timer for generating replica timing pulses to permit reading of the phase and frequency information received from the master PLL device, said replica synchronization timer being responsive to timing pulses received from the master PLL device to synchronize said replica synchronization timer with a master synchronization timer in the master PLL device. ### Claim 12 (depends on 11) The slave device as claimed in claim 11, further comprising a peripheral interface for receiving said phase and frequency information from the master PLL device. ### Claim 13 (depends on 11) The slave device as claimed in claim 11, further comprising an edge detector for detecting an edge of the timing pulses received from the master PLL device to define an alignment point for synchronizing said replica synchronization timer with said master synchronization timer. ### Claim 14 A method of controlling one or more slave devices each including a respective first digitally controlled oscillator (DCO) controlled by an output of a second DCO in a master phase locked loop device, comprising: generating timing pulses in the master phase locked loop device by a master synchronization timer; synchronizing at least one replica synchronization timer with master timing pulses received from said master phase locked loop device; reading phase and frequency information from said output of said second DCO; transmitting said read phase and frequency information to said one or more slave devices over a peripheral interface; and updating the first DCO in the respective slave device of the one or more slave devices with said transmitted phase and frequency information based on timing pulses generated by said at least one replica synchronization timer. ### Claim 15 (depends on 14) The method as claimed in claim 14, wherein said synchronizing occurs upon initialization or whenever a count value in the master synchronization timer is changed. ### Claim 16 (depends on 14) The method as claimed in claim 14, wherein said master timing pulses have a width that is wide enough to guarantee correct sampling by said one or more slave devices. ### Claim 17 (depends on 14) The method as claimed in claim 14, wherein the master phase locked loop device comprises a plurality of phase locked loop (PLL) channels, each PLL channel including a respective DCO, and a selected one of said PLL channels is designated as a feedback channel, the method further comprising sending a feedback signal from a selected one of the slave devices to said feedback channel to develop a fine alignment value for transmission to said selected one of the slave devices. ### Claim 18 (depends on 17) The method as claimed in claim 17, further comprising updating the respective DCO of the non-selected one or more PLL channels based on said feedback signal. ### Claim 19 (depends on 17) The method as claimed in claim 17, wherein said one or more slave devices are selected in turn based on a feedback signal. ### Claim 20 A system comprising: a master phase locked loop device working in association with one or more slave devices including at least one slave digitally controlled oscillator (sDCO), the master PLL device comprising: at least one digital PLL (DPLL) channel including a master digitally controlled oscillator (mDCO) having a higher resolution than said at least one sDCO; a master synchronization timer for generating master timing pulses to permit reading phase and frequency information from said mDCO; a peripheral interface for sending said read frequency and phase information to said one or more slave devices; and a master synchronization interface for sending said master timing pulses to synchronize a replica synchronization timer in said at least one sDCO that generates slave timing pulses for use in updating said phase and frequency information received at said one or more slave devices; wherein said one or more slave devices, comprise: a slave digitally controlled oscillator controlled by phase and frequency information obtained from the master PLL device; and a replica synchronization timer for generating replica timing pulses to permit reading of phase and frequency information received from the master PLL device, said replica synchronization timer being responsive to timing pulses received from the master PLL device to synchronize said replica synchronization timer with said synchronization timer in the master device.