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US 10,003,302 B2Granted
Modified tunneling field effect transistors and fabrication methods
AssigneeGlobalfoundries Inc.
InventorsYanxiang Liu, Min-hwa Chi
Life of this patent
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Abstract
Tunneling field effect transistors and fabrication methods thereof are provided, which include: an integrated circuit device which includes a circuit input configured to receive an input voltage and a circuit output configured to deliver an output current. The integrated circuit also includes a circuit element having at least one tunneling field effect transistor (TFET). The circuit element connects the circuit input to the circuit output and is characterized by a V-shaped current-voltage diagram. The V-shaped current-voltage diagram describes the relationship between the input voltage of the circuit input and the output current of the circuit output.
Claims14
An integrated circuit device comprising:
- a circuit input configured to receive an input voltage;
- a circuit output configured to deliver an output current;
- and
- a circuit element comprising one tunneling field effect transistor (TFET), the TFET comprising:
- a source region being one of an n-type and a p-type and having a source region band gap defined by a source region valence band and a source region conduction band,
- a drain region being the other of the n-type and p-type and having a drain region band gap defined by a drain region valence band and a drain region conduction band,
- a channel region separating the source and drain regions, the channel region having a channel region band gap defined by a channel region valence band and a channel region conduction band, and
- a gate disposed over the channel region, the gate overlapping the source region and drain region to form a source region junction and a drain region junction,
- wherein the source region band gap and drain region band gap are at least 60 meV narrower than the channel region band gap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers between at least one of the region valence bands and at least one of the region conduction bands such that the charge carriers conduct from the source region or the drain region to the channel region;
- the circuit element connecting the circuit input to the circuit output and being characterized by a V-shaped current-voltage diagram, the V-shaped current-voltage diagram describing the relationship between the input voltage of the circuit input and the output current of the circuit output, the V-shaped current-voltage diagram comprising a positive sloped branch and a negative sloped branch.
7 more elements
A tunneling field effect transistor (TFET), comprising:
- a gate disposed over a substrate structure;
- a source region disposed within the substrate structure, the source region being one of an n-type and a p-type, the source region having a source region band gap defined by a source region valence band and a source region conduction band;
- a drain region disposed within the substrate structure, the drain region being the other of the n-type and the p-type the drain region having a drain region band gap defined by a drain region valence band and a drain region conduction band;
- a channel region disposed within the substrate structure between the source and drain regions, the channel region underlying, at least partially, the gate, the channel region having a channel region band gap defined by a channel region valence band and a channel region conduction band, wherein the source region band gap and drain region band gap are at least 60 meV narrower than the channel region band gap, the narrowed source region band gap and the narrowed drain region band gap facilitating quantum tunneling of charge carriers between at least one of the region valence bands and at least one of the region conduction bands such that the charge carriers conduct from the source region or the drain region to the channel region;
- a source region junction defined by an overlap of the source region with the gate wherein tunneling of one of an n-type and a p-type charge carrier occurs;
- and
- a drain region junction defined by an overlap of the drain region with the gate wherein tunneling of the other of the n-type and the p-type charge carrier occurs;
- wherein the tunneling of the n-type and p-type charge carriers is characterized by a V-shaped current-voltage diagram of the TFET.
5 more elements
Dependencies are inferred from the claim text.