Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsTakahiro Shimizu, Noboru Shibata, Hiroshi Maejima
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes first and second memory cell arrays, and first and second control circuits configured to execute an operation on the first and second memory cell arrays. The first control circuit executes an operation on the first memory cell array responsive to a first command set that is received by the semiconductor memory device. The second control circuit executes an operation on the second memory cell array responsive to second and third command sets that are received by the semiconductor memory device while the first control circuit is executing the operation on the first memory cell array.
Claims18
A semiconductor memory device comprising:
- first and second memory cell arrays;
- and
- first and second control circuits configured to execute an operation on the first and second memory cell arrays, wherein
- the first control circuit executes an operation on the first memory cell array responsive to a first command set that is received by the semiconductor memory device, and
- the second control circuit executes an operation on the second memory cell array responsive to second and third command sets that are received by the semiconductor memory device while the first control circuit is executing the operation on the first memory cell array, and wherein
- the second control circuit is in an idle state at the time the second command set is received and the second control circuit transitions from the idle state to an active state responsive to the second command set.
A method of performing a multi-plane operation in a semiconductor memory device including first and second memory cell arrays, said method comprising:
- receiving a first command set;
- executing an operation on the first memory cell array in accordance with the first command set;
- and
- receiving a second command set and executing an operation on the second memory cell array in accordance with the second command set, while the operation on the first memory cell array is being executed, wherein
- the first command set includes a read command and an address designating the first memory cell array, and the second command set includes a read command and an address designating the second memory cell array.
Dependencies are inferred from the claim text.