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US 10,002,665 B1Granted
Memory devices formed from correlated electron materials
AssigneeArm Limited
InventorsMudit Bhargava, Piyush Agarwal, Akshay Kumar, Glen Arnold Rosendale
Life of this patent
Estimating the term…
Abstract
Subject matter provided may relate to devices, such as conducting elements, which operate to place correlated electron switch elements into first and second impedance states. In embodiments, conducting elements are maintained to be at least partially closed continuously during first and second phases of coupling the CES elements between a common source voltage and a corresponding bitline.
Claims21
A method comprising:
- applying a first voltage to first terminals of a plurality of conducting elements, each of the plurality of conducting elements being configured to couple a corresponding correlated electron switch (CES) element of a plurality of CES elements, between a common source voltage and one of a plurality of bitlines during a first phase of an operation to place one or more first ones of the plurality of CES elements into a first impedance state;
- and
- applying a second voltage to the first terminals of the plurality of conducting elements during a second phase of the operation to place one or more second ones of the plurality of CES elements into a second impedance state, wherein the second voltage applied to the first terminals of the plurality of conducting elements is selected to limit current to determine a condition of a current density in the one or more second ones of the plurality of CES elements for a subsequent operation to place the one or more second ones of the plurality of CES elements into a high-impedance or insulative state,
- wherein the plurality of conducting elements are in an at least partially closed state continuously during the first and second phases to couple each of the CES elements between the common source voltage and a corresponding one of the plurality of bitlines.
1 more element
A method comprising:
- applying a first voltage to first terminals of a plurality of conducting elements, one or more first ones of the plurality of conducting elements being configured to couple one or more first correlated electron switch (CES) elements between a first bitline voltage and a first common source voltage, one or more second ones of the plurality of conducting elements being configured to couple one or more second CES elements between a second bitline voltage and a second common source voltage;
- and
- limiting a current in the one or more first CES elements to determine a condition of a current density in the one or more second ones of the plurality of CES elements for a subsequent operation to place the one or more second ones of the plurality of CES elements into a relatively high-impedance or insulative state,
- wherein the one or more first CES elements are placed into a first impedance state and the one or more second CES elements are placed into a second impedance state while continuously maintaining an approximately constant voltage difference between the first bitline voltage and the first common source voltage or the second common source voltage.
1 more element
A device comprising:
- a plurality of bitcells, each of the bitcells comprising a first terminal coupled to a common source voltage and a second terminal coupled to a bitline corresponding to a memory element of the plurality of bitcells;
- and
- a driver circuit to apply a first voltage to first terminals of conducting elements of each of the plurality of bitcells, the conducting elements being configured to couple a corresponding correlated electron switch (CES) element of each of the plurality of bitcells, among a plurality of CES elements, between a common source voltage and the bitline corresponding to a memory element in a first phase of an operation to place one or more of the plurality of CES elements into a first impedance state;
- and
- the driver circuit to apply a second voltage to the first terminals of the conducting elements of each of the plurality of bitcells in a second phase of the operation to place one or more second ones of the plurality of CES elements into a second impedance state, the second voltage to apply to the first terminals of the conducting elements to be selected to limit current to determine a condition of a current density in the one or more second ones of the plurality of CES elements for a subsequent operation to place the one or more second ones of the plurality of CES elements into a relatively high-impedance or insulative state,
- wherein the conducting elements of each of the plurality of bitcells are at least partially closed during the first and second phases to couple each of the CES elements between the common source voltage and the bitline corresponding to the memory element.
3 more elements
Dependencies are inferred from the claim text.